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LM124-LM224-LM324
Low Power Quad Operational Amplifiers

Wide gain bandwidth: 1.3MHz Input common-mode voltage range includes ground Large voltage gain: 100dB Very low supply current/ampli: 375A Low input bias current: 20nA Low input offset voltage: 5mV max. (for more accurate applications, use the equivalent parts LM124A-LM224A-LM324A which feature 3mV max.) Low input offset current: 2nA Wide power supply range: Single supply: +3V to +30V Dual supplies: 1.5V to 15V D SO-14 (Plastic Micropackage) N DIP14 (Plastic Package)

Description
These circuits consist of four independent, high gain, internally frequency compensated operational amplifiers. They operate from a single power supply over a wide range of voltages. Operation from split power supplies is also possible and the low power supply current drain is independent of the magnitude of the power supply voltage. P TSSOP-14 (Thin Shrink Small Outline Package)
Order Codes
Part Number LM124N LM124D/DT LM224N LM224D/DT LM224PT LM324N LM324D/DT LM324PT Temperature Range -55C, +125C Package DIP SO DIP SO TSSOP (Thin Shrink Outline Package) DIP SO TSSOP (Thin Shrink Outline Package) Packaging Tube Tube or Tape & Reel Tube Tube or Tape & Reel Tape & Reel Tube Tube or Tape & Reel Tape & Reel
-40C, +105C
0C, +70C
June 2005
Rev 3 1/16
www.st.com
16
Absolute Maximum Ratings
LM124-LM224-LM324
1
Absolute Maximum Ratings
Table 1.
Symbol VCC Vi Vid Ptot Supply voltage Input Voltage Differential Input Voltage (1) Power Dissipation N Suffix D Suffix Output Short-circuit Duration (2) Iin Toper Tstg Input Current (3) Operating Free-air Temperature Range Storage Temperature Range Thermal Resistance Junction to Ambient SO14 TSSOP14 DIP14 HBM: Human Body Model(4) ESD MM: Machine Model(5) CDM: Charged Device Model
1. Either or both input voltages must not exceed the magnitude of VCC or
+
15Key parameters and their absolute maximum ratings
Parameter LM124 LM224 16 or 32 -0.3 to Vcc + 0.3 -0.3 to Vcc + 0.3 500 500 400 Infinite 50 50 50 mA C C 500 400 LM324 Unit V V V mW
-55 to +125 -40 to +105 0 to +70 -65 to +150 103 100 66 250 150 1500
VCC-.
Rthja
C/W
V
2. Short-circuits from the output to VCC can cause excessive heating if VCC > 15V. The maximum output current is approximately 40mA independent of the magnitude of VCC. Destructive dissipation can result from simultaneous short-circuit on all amplifiers. 3. This input current only exists when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistor becoming forward biased and thereby acting as input diodes clamps. In addition to this diode action, there is also NPN parasitic action on the IC chip. this transistor action can cause the output voltages of the op-amps to go to the VCC voltage level (or to ground for a large overdrive) for the time duration than an input is driven negative. This is not destructive and normal output will set up again for input voltage higher than -0.3V. 4. Human body model, 100pF discharged through a 1.5k resistor into pin of device. 5. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (internal resistor < 5), into pin to pin of device.
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LM124-LM224-LM324
Pin & Schematic Diagram
2
Pin & Schematic Diagram
Figure 1. Pin connections (top view)
Output 1 1 Inverting Input 1 2 Non-inverting Input 1 3 VCC + 4 Non-inverting Input 2 Inverting Input 2 5 6 + + + +
14 Output 4 13 Inverting Input 4 12 Non-inverting Input 4 11 VCC 10 Non-inverting Input 3 9 Inverting Input 3 8 Output 3
Output 2 7
Figure 2.
Schematic diagram (1/4 LM124)
3/16
Electrical Characteristics
LM124-LM224-LM324
3
Electrical Characteristics
Table 2.
Symbol
VCC+ = +5V, VCC-= Ground, Vo = 1.4V, Tamb = +25C (unless otherwise specified)
Parameter Input Offset Voltage - note Tamb = +25C Tmin T amb T max Input Offset Current Tamb = +25C Tmin T amb T max Input Bias Current - note (2) Tamb = +25C Tmin T amb T max Large Signal Voltage Gain VCC+ = +15V, RL = 2k, Vo = 1.4V to 11.4V Tamb = +25C Tmin T amb T max Supply Voltage Rejection Ratio (Rs 10k) VCC+ = 5V to 30V Tamb = +25C Tmin T amb T max Supply Current, all Amp, no load Tamb = +25C V CC = +5V VCC = +30V Tmin T amb T max V CC = +5V V CC = +30V Input Common Mode Voltage Range VCC = +30V - note (3) Tamb = +25C Tmin T amb T max Common Mode Rejection Ratio (Rs 10k) Tamb = +25C Tmin Tamb Tmax Output Current Source (V id = +1V) VCC = +15V, Vo = +2V Output Sink Current (Vid = -1V) VCC = +15V, Vo = +2V VCC = +15V, Vo = +0.2V High Level Output Voltage VCC = +30V Tamb = +25C Tmin T amb T max Tamb = +25C Tmin T amb T max VCC = +5V, R L = 2k Tamb = +25C Tmin T amb T max
(1)
Min.
Typ. 2
Max. 5 7 7 9 30 100 150 300
Unit
Vio
LM324 LM324
mV
Iio
2
nA
Iib
20
nA
Avd
50 25
100
V/mV
SVR
65 65
110
dB
ICC
0.7 1.5 0.8 1.5
1.2 3 1.2 3
mA
Vicm
0 0 70 60 20 10 12 80
VCC -1.5 VCC -2
V
CMR
dB
Isource Isink
40 20 50
70
mA
mA A V
RL = 2k R L = 10k
VOH
26 26 27 27 3.5 3
27 28
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LM124-LM224-LM324
Table 2.
Symbol VOL
Electrical Characteristics
VCC+ = +5V, VCC-= Ground, Vo = 1.4V, Tamb = +25C (unless otherwise specified)
Parameter Low Level Output Voltage (RL = 10k) Tamb = +25C Tmin T amb T max Slew Rate VCC = 15V, V i = 0.5 to 3V, RL = 2k, CL = 100pF, unity Gain Gain Bandwidth Product VCC = 30V, f =100kHz,V in = 10mV, R L = 2k, CL = 100pF Total Harmonic Distortion f = 1kHz, Av = 20dB, RL = 2k, Vo = 2V pp, CL = 100pF, VCC = 30V Equivalent Input Noise Voltage f = 1kHz, Rs = 100, VCC = 30V Input Offset Voltage Drift Input Offset Current Drift Channel Separation - note (4) 1kHz f 20kHZ Min. Typ. 5 Max. 20 20 Unit mV
SR GBP
0.4 1.3
V/s MHz
THD en DVio DIIio Vo1/Vo2
0.015
%
nV ----------Hz
40 7 10 120 30 200
V/ C pA/ C dB
1. Vo = 1.4V, Rs = 0, 5V < VCC + < 30V, 0 < Vic < VCC+ - 1.5V 2. The direction of the input current is out of the IC. This current is essentially constant, independent of the state of the output so no loading change exists on the input lines. 3. The input common-mode voltage of either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is VCC+ - 1.5V, but either or both inputs can go to +32V without damage. 4. Due to the proximity of external components insure that coupling is not originating via stray capacitance between these external parts. This typically can be detected as this type of capacitance increases at higher frequencies.
Table 3.
Symbol Vio Avd Icc Vicm VOH VOL Ios GBP SR
Vcc+ = +15V, Vcc- = 0V, Tamb = 25C (unless otherwise specified)
Conditions RL = 2k No load, per amplifier
+=15V)
Value 0 100 350 -15 to +13.5
Unit mV V/mV A V V mV mA MHz V/s
RL = 2k (VCC RL = 10k
+13.5 5 +40 1.3 0.4
Vo = +2V, VCC = +15V RL = 2k, CL = 100pF RL = 2k, CL = 100pF
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Electrical Characteristics
Figure 3. Input bias current vs. ambient temperature
INPUT BIAS CURRENT versus AMBIENT TEMPERATURE
IB (nA)
LM124-LM224-LM324
Figure 4. Current limiting
24 21 18 15 12 9 6 3 0
-55-35-15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE (C)
Figure 5.
Input voltage range
Figure 6.
Supply current
Figure 7.
Gain bandwidth product
Figure 8.
Common mode rejection ratio
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LM124-LM224-LM324
Figure 9. Electrical curves
Electrical Characteristics
7/16
Electrical Characteristics
Figure 10. Input current
LM124-LM224-LM324
Figure 11. Large signal voltage gain
Figure 12. Power supply & common mode rejection ratio
Figure 13. Voltage gain
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LM124-LM224-LM324
Typical Single - Supply Applications
4
Typical Single - Supply Applications
Figure 15. High input Z adjustable gaind DC instrumentation amplifier
Figure 14. AC coupled inverting amplifier
if R1 = R5 and R3 = R4 = R6 = R7
1 e0 = 1 + ----------- (e2 -e1) R 2 2R
As shown e0 = 101 (e2 - e1).
Figure 16. AC coupled non inverting amplifier
Figure 17. DC summing amplifier
e0 = e1 +e2 -e3 -e4 Where (e1 +e2) (e3 +e4) to keep e0 0V
Figure 18. Non-inverting DC gain
Figure 19. Low drift peak detector
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Typical Single - Supply Applications
Figure 20. Activer bandpass filter
LM124-LM224-LM324
Figure 21. High input Z, DC differential amplifier
R R 1 4 For ------- = -----R R 2 3 (CMRR depends on this resistor ratio match)
Fo = 1kHz Q = 50 Av = 100 (40dB)
e0
1 + R 4 ------ R 3
(e2 - e1)
As shown e0 = (e2 - e1)
Figure 22. Using symmetrical amplifiers to reduce input current (general concept)
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LM124-LM224-LM324
Macromodels
5
Note:
Macromodels
Note: Please consider following remarks before using this macromodel: All models are a trade-off between accuracy and complexity (i.e. simulation time). Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a design approach and help to select surrounding component values. A macromodel emulates the NOMINAL performance of a TYPICAL device within SPECIFIED OPERATING CONDITIONS (i.e. temperature, supply voltage, etc.). Thus the macromodel is often not as exhaustive as the datasheet, its goal is to illustrate the main parameters of the product. Data issued from macromodels used outside of its specified conditions (Vcc, Temperature, etc.) or even worse: outside of the device operating conditions (Vcc, Vicm, etc.) are not reliable in any way.
** Standard Linear Ics Macromodels, 1993. ** CONNECTIONS : * 1 INVERTING INPUT * 2 NON-INVERTING INPUT * 3 OUTPUT * 4 POSITIVE POWER SUPPLY * 5 NEGATIVE POWER SUPPLY .SUBCKT LM124 1 3 2 4 5 (analog) ******************************************************* .MODEL MDTH D IS=1E-8 KF=3.104131E-15 CJO=10F * INPUT STAGE CIP 2 5 1.000000E-12 CIN 1 5 1.000000E-12 EIP 10 5 2 5 1 EIN 16 5 1 5 1 RIP 10 11 2.600000E+01 RIN 15 16 2.600000E+01 RIS 11 15 2.003862E+02 DIP 11 12 MDTH 400E-12 DIN 15 14 MDTH 400E-12 VOFP 12 13 DC 0 VOFN 13 14 DC 0 IPOL 13 5 1.000000E-05 CPS 11 15 3.783376E-09 DINN 17 13 MDTH 400E-12 VIN 17 5 0.000000e+00 DINR 15 18 MDTH 400E-12 VIP 4 18 2.000000E+00 FCP 4 5 VOFP 3.400000E+01 FCN 5 4 VOFN 3.400000E+01 FIBP 2 5 VOFN 2.000000E-03 FIBN 5 1 VOFP 2.000000E-03 * AMPLIFYING STAGE FIP 5 19 VOFP 3.600000E+02
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Macromodels
FIN 5 19 VOFN 3.600000E+02 RG1 19 5 3.652997E+06 RG2 19 4 3.652997E+06 CC 19 5 6.000000E-09 DOPM 19 22 MDTH 400E-12 DONM 21 19 MDTH 400E-12 HOPM 22 28 VOUT 7.500000E+03 VIPM 28 4 1.500000E+02 HONM 21 27 VOUT 7.500000E+03 VINM 5 27 1.500000E+02 EOUT 26 23 19 5 1 VOUT 23 5 0 ROUT 26 3 20 COUT 3 5 1.000000E-12 DOP 19 25 MDTH 400E-12 VOP 4 25 2.242230E+00 DON 24 19 MDTH 400E-12 VON 24 5 7.922301E-01 .ENDS
LM124-LM224-LM324
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LM124-LM224-LM324
Package Mechanical Data
6
Package Mechanical Data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
6.1
DIP14 Package
Plastic DIP-14 MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001A
13/16
Package Mechanical Data
LM124-LM224-LM324
6.2
SO-14 Package
SO-14 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13G
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LM124-LM224-LM324
Package Mechanical Data
6.3
TSSOP14 Package
TSSOP14 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
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Revision History
LM124-LM224-LM324
7
Revision History
Date Oct. 2003 Jan. 2005 June 2005 Revision 1 2 3 First Release Modifications on AMR Table 1 on page 2 (explanation of Vid and Vi limits) ESD protection inserted in Table 1 on page 2 Changes
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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